PL138-48OI-R datasheet(6/20 Pages) MICROCHIP

부품명	PL138-48OI-R

상세설명	2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer

PDF	20 Pages

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제조업체	MICROCHIP [Microchip Technology]

홈페이지	http://www.microchip.com

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6 / 20 page

PL138-48

DS20005543B-page 6

 2016 Microchip Technology Inc.

2.0

PIN DESCRIPTIONS

FIGURE 2-1:

Pin Configuration, 16-Pin QFN.

FIGURE 2-2:

Pin Configuration, 20-Pin TSSOP.

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

QFN-16

Pin Number

TSSOP-20

Pin Name

Type

Description

VEE

Power supply pin connection.

CLK-EN

Synchronizing clock enable.

When HIGH, clock outputs follow clock input. When LOW, Q

outputs are forced low, QB outputs are forced high.

LVTTL/LVCMOS interface levels.

50 kΩ internal pull-up resistor.

—

CLK-SEL

Clock select input. When HIGH, selects CLK1 input. When

LOW, selects CLK0 input.

LVTTL/LVCMOS interface levels.

50 kΩ internal pull-down resistor.

CLK-IN0

True part of differential clock input signal. 75 kΩ internal

pull-down resistor.

CLK-IN0B

Complementary part of differential clock input signal.

100 kΩ internal pull-up and pull-down resistors.

PL138-48OI-R 데이터시트(PDF) 6 Page - Microchip Technology