EM351-RTR datasheet(55/241 Pages) SILABS

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Rev 1.3



The Schmitt trigger input is connected to the pin.



Reading GPIO_PxIN returns the input at the pin.

Note:

Reading GPIO_PxOUT returns the last value written to the register.



Depending on configuration and usage, GPIO_PxOUT and GPIO_PxIN may not have the same value.

7.6.4. Alternate Output Mode

In this mode, the output is controlled by an on-chip peripheral instead of GPIO_PxOUT and may be configured as

either push-pull or open-drain. Most peripherals require a particular output type – TWI requires an open-drain

driver, for example – but since using a peripheral does not by itself configure a pin, the GPIO_PxCFGH/L registers

must be configured properly for a peripheral’s particular needs. As described in "7.2. Configuration" on page 51,

when more than one peripheral can be the source of output data, registers in addition to GPIO_PxCFGH/L

determine which to use.

When configured in alternate output mode:



The output drivers are enabled and are controlled by the output of an on-chip peripheral:



In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the pin.



In push-pull mode: 0 activates the N-MOS current sink; 1 activates the P-MOS current source.



The internal pull-up and pull-down resistors are disabled.



The Schmitt trigger input is connected to the pin.

Note:

Reading GPIO_PxIN returns the input to the pin.



Depending on configuration and usage, GPIO_PxOUT and GPIO_PxIN may not have the same value.

7.7. Wake Monitoring

The GPIO_PxWAKE registers specify which GPIOs are monitored to wake the processor. If a GPIO’s wake enable

bit is set in GPIO_PxWAKE, then a change in the logic value of that GPIO causes the EM35x to wake from deep

sleep. The logic values of all GPIOs are captured by hardware upon entering sleep. If any GPIO’s logic value

changes while in sleep and that GPIO’s GPIO_PxWAKE bit is set, then the EM35x wakes from deep sleep. (There

is no mechanism for selecting a specific rising-edge, falling-edge, or level on a GPIO: any change in logic value

triggers a wake event.) Hardware records the fact that GPIO activity caused a wake event, but not which specific

GPIO was responsible. Instead, the Ember software reads the state of the GPIOs on waking to determine this.

The register GPIO_WAKEFILT contains bits to enable digital filtering of the external wakeup event sources: the

GPIO pins, SC1 activity, SC2 activity, and IRQD. The digital filter operates by taking samples based on the

(nominal) 10 kHz RC oscillator. If three samples in a row all have the same logic value, and this sampled logic

value is different from the logic value seen upon entering sleep, the filter outputs a wakeup event.

In order to use GPIO pins to wake the EM35x from deep sleep, the GPIO_WAKE bit in the WAKE_SEL register

must be set. Waking up from GPIO activity does not work with pins configured for analog mode since the digital

logic input is always set to 1 when in analog mode. Refer to "6. System Modules" on page 35 for information on the

EM35x’s power management and sleep modes.

7.8. External Interrupts

The EM35x can use up to four external interrupt sources (IRQA, IRQB, IRQC, and IRQD), each with its own top-

level NVIC interrupt vector. Since these external interrupt sources connect to the standard GPIO input path, an

external interrupt pin may simultaneously be used by a peripheral device or even configured as an output. Analog

mode is the only GPIO configuration that is not compatible with using a pin as an external interrupt.

External interrupts have individual triggering and filtering options selected using the registers GPIO_INTCFGA,

GPIO_INTCFGB, GPIO_INTCFGC, and GPIO_INTCFGD. The bit field GPIO_INTMOD of the GPIO_INTCFGx

falling edge; 3 for both edges; 4 for active high level; 5 for active low level. The minimum width needed to latch an

unfiltered external interrupt in both level- and edge-triggered mode is 80 ns. With the digital filter enabled (the

GPIO_INTFILT bit in the GPIO_INTCFGx register is set), the minimum width needed is 450 ns.

The register INT_GPIOFLAG is the second-level interrupt flag register that indicates pending external interrupts.

Writing 1 to a bit in the INT_GPIOFLAG register clears the flag while writing 0 has no effect. If the interrupt is level-

triggered, the flag bit is set again immediately after being cleared if its input is still in the active state.

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