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EM351-RTR 데이터시트(PDF) 106 Page - Silicon Laboratories |
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EM351-RTR 데이터시트(HTML) 106 Page - Silicon Laboratories |
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106 / 241 page ![]() Rev 1.3 106 SC1_TXENDB: Address: 0x4000C81C Reset: 0x20000000 SC2_TXENDB: Address: 0x4000C01C Reset: 0x20000000 SC1_TXCNT: Address: 0x4000C828 Reset: 0x0 SC2_TXCNT: Address: 0x4000C028 Reset: 0x0 Register 8.22. SCx_TXENDB SC1_TXENDB: Transmit DMA End Address Register B SC2_TXENDB: Transmit DMA End Address Register B Bit 31 30 29 28 27 26 25 24 Name 0 0 1 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 SC_TXENDB Bit 7 6 5 4 3 2 1 0 Name SC_TXENDB Bitname Bitfield Access Description SC_TXENDB [13:0] RW Address of the last byte that will be read from the DMA transmit buffer B. Register 8.23. SCx_TXCNT SC1_TXCNT: Transmit DMA Count Register SC2_TXCNT: Transmit DMA Count Register Bit 31 30 29 28 27 26 25 24 Name 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Name 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Name 0 0 SC_TXCNT Bit 7 6 5 4 3 2 1 0 Name SC_TXCNT Bitname Bitfield Access Description SC_TXCNT [13:0] R The offset from the start of the active DMA transmit buffer from which the next byte will be read. This register is set to zero when the buffer is loaded and when the DMA is reset. |
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