EM351-RTR datasheet(138/241 Pages) SILABS

138 / 241 page

Rev 1.3

138

Figure 9.29. Control Circuit in Trigger Mode

9.3.13.4. Slave Mode: External Clock Mode 2 +Trigger Mode

External clock mode 2 can be used in combination with another slave mode (except external clock mode 1 and

encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as

trigger input when operating in reset mode, gated mode or trigger mode. It is not recommended to select ETR as

TRGI through the TIM_TS bits of TIMx_SMCR register.

In the following example (shown in Figure 9.30) the up-counter is incremented at each rising edge of the ETR

signal as soon as a rising edge of TI1 occurs:



Configure the external trigger input circuit: Program the TIMx_SMCR register as follows:



TIM_ETF = 0000: no filter.



TIM_ETPS = 00: prescaler disabled.



TIM_ETP = 0: detection of rising edges on ETR and TIM_ECE = 1 to enable the external clock mode 2.



Configure the channel 1 to detect rising edges on TI, as follows:



TIM_IC1F = 0000: no filter.



The capture prescaler is not used for triggering and does not need to be configured.



TIM_CC1S = 01 in the TIMx_CCMR1 register to select only the input capture source.



TIM_CC1P = 0 in the TIMx_CCER register to validate the polarity (and detect rising edge only).



Configure the timer in trigger mode: WriteTIM_SMS = 110 in the TIMx_SMCR register.



Select TI1 as the input source by writing TIM_TS = 101 in the TIMx_SMCR register.

A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then counts on ETR rising

edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the

resynchronization circuit on ETRP input.

Figure 9.30. Control Circuit in External Clock Mode 2 + Trigger Mode

EM351-RTR 데이터시트(PDF) 138 Page - Silicon Laboratories