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EM351-RTR 데이터시트(PDF) 147 Page - Silicon Laboratories

부품명 EM351-RTR
상세설명  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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제조업체  SILABS [Silicon Laboratories]
홈페이지  http://www.silabs.com
Logo SILABS - Silicon Laboratories

EM351-RTR 데이터시트(HTML) 147 Page - Silicon Laboratories

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147
Rev 1.3
TIM1_CR2: Address: 0x4000E004 Reset: 0x0
TIM2_CR2: Address: 0x4000F004 Reset: 0x0
Register 9.2. TIMx_CR2
TIM1_CR2: Timer 1 Control Register 2
TIM2_CR2: Timer 2 Control Register 2
Bit
31
30
29
28
27
26
25
24
Name
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Name
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
TIM_TI1S
TIM_MMS
0
0
0
0
Bitname
Bitfield
Access
Description
TIM_TI1S
[7]
RW
TI1 Selection.
0: TI1M (input of the digital filter) is connected to TI1 input.
1: TI1M is connected to the TI_HALL inputs (XOR combination).
TIM_MMS
[6:4]
RW
Master Mode Selection.
This selects the information to be sent in master mode to a slave timer for syn-
chronization using the trigger output (TRGO).
000: Reset - the TIM_UG bit in the TMRx_EGR register is trigger output.
If the reset is generated by the trigger input (slave mode controller configured in
reset mode), then the signal on TRGO is delayed compared to the actual reset.
001: Enable - counter enable signal CNT_EN is trigger output.
This mode is used to start both timers at the same time or to control a window in
which a slave timer is enabled. The counter enable signal is generated by
either the TIM_CEN control bit or the trigger input when configured in gated
mode. When the counter enable signal is controlled by the trigger input there is
a delay on TRGO except if the master/slave mode is selected (see the
TIM_MSM bit description in TMRx_SMCR register).
010: Update - UEV is trigger output.
This mode allows a master timer to be a prescaler for a slave timer.
011: Compare Pulse.
The trigger output sends a positive pulse when the TIM_CC1IF flag is to be set
(even if it was already high) as soon as a capture or a compare match occurs.
100: Compare - OC1REF signal is trigger output.
101: Compare - OC2REF signal is trigger output.
110: Compare - OC3REF signal is trigger output.
111: Compare - OC4REF signal is trigger output.



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