PC87351 datasheet(49/86 Pages) NSC

49 / 86 page

2.0 Device Architecture and Configuration (Continued)

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2.13

FAN SPEED CONTROL - LOGICAL DEVICE 8

2.13.1

General Description

This module includes two Fan Speed Controls. The four runtime registers of the two functional blocks are arranged in the

address space shown in Table 2-13. The base address is 8-byte aligned. Address bits 2-0 are used to indicate the register

offset.

2.13.2

Configuration

Table 2-13. Runtime Registers in Fan Speed Control Address Space

Offset

Mnemonic

Name

Reset

Function

Type

00h

FCPSR0

Fan Control 0 Pre-Scale Register

00h

Fan Speed Control 0

R/W

01h

FCDCR0

Fan Control 0 Duty Cycle Register

FFh

R/W

02h

FCPSR1

Fan Control 1 Pre-Scale Register

00h

Fan Speed Control 1

R/W

03h

FCDCR1

Fan Control 1 Duty Cycle Register

FFh

R/W

04h-07h Reserved

Table 2-14. Fan Speed Control Runtime Register Bitmap

Bits

Offset

Mnemonic

00h

FCPSR0

Clock

Select

Pre-Scale Value

01h

FCDCR0

Duty Cycle Value

02h

FCPSR1

Clock

Select

Pre-Scale Value

03h

FCDCR1

Duty Cycle Value

04h-

07h

Reserved

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1 Register.

R/W

00h

60h

Base Address MSB Register

R/W

00h

61h

Base Address LSB Register. Bits 2-0 (for A2-0) are read only, 000b.

R/W

00h

70h

Interrupt Number

00h

71h

Interrupt Type

00h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

Fan Speed Control Conﬁguration Register

R/W

00h

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