PC87351 datasheet(23/86 Pages) NSC

23 / 86 page

1.0 Signal/Pin Connection and Description (Continued)

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1.4.10

Serial Ports 1 and 2

1.4.11

Strapping

1.4.12

System Wake-Up Control

Signal

Pin/s

I/O

Buffer Type

Description

CTS1,

CTS2

109,

118

IINTS

Clear to Send. When low, indicate that the modem or other data transfer

device is ready to exchange data.

DCD1,

DCD1

IINTS

Data Carrier Detected. When low, indicate that the modem or other data

transfer device has detected the data carrier.

DSR1,

DSR2

105,

113

IINTS

Data Set Ready. When low, indicate that the data transfer device, e.g.,

modem, is ready to establish a communications link.

DTR1/

BOUT1,

DTR2/

BOUT2

110,

119

OO6/12

Data Terminal Ready. When low, indicate to the modem or other data

transfer device that the Serial Port is ready to establish a communications

link. After system reset, these pins provides the DTR function, sets these

signals to inactive high, and loopback operation holds them inactive.

Baud Output. Provides the associated serial channel baud rate generator

output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is

set.

DTR1/BOUT1 is used also as BADDR.

RI1,

RI2

111,

120

IINTS

Ring Indicators (Modem). When low, indicate that a telephone ring signal

has been received by the modem. These pins may issue wake-up event.

RTS1,

RTS2

107,

115

OO6/12

Request to Send. When low, indicate to the modem or other data transfer

device that the corresponding Serial Port is ready to exchange data. A

system reset sets these signals to inactive high, and loopback operation

holds them inactive.

SIN1,

SIN2

106,

114

IINTS

Serial Input. Receive composite serial data from the communications link

(peripheral device, modem or other data transfer device).

SOUT1,

SOUT2

108,

117

OO6/12

Serial Output. Send composite serial data to the communications link

(peripheral device, modem or other data transfer device). The SOUT2,1

signals are set active high after system reset.

Signal

Pin/s

I/O

Buffer Type

Description

BADDR

110

INSTRP

Base Address Strap. Determines the base address of the Index and Data

registers. It is pulled down by an internal 30 Kohm resistor to get base

address 2Eh for the Index register, and 2Fh for the Data register. If the

respective base addresses are 15Ch and 15Dh, use an external 10 Kohm

pull-up resistor (to VDD).

Signal

Pin/s

I/O

Buffer Type

Description

PME1,

PME2

125,

126

IINTS

Power Management Event 1, 2. Detection of an event on PME1 or PME2

may activate the PWUREQ signal (wake-up event).

PWUREQ

124

OD6/12

Power Up Request. Low level (active) indicates that wake-up event has

occurred. This may cause the chipset to turn the power supply on, or to

exit its current sleep state. The open-drain output must be pulled up to

VSB, in order to function during power-off.

RING

125

INTS

Telephone Line Ring. Detection of a pulse-train on the RING pin, is a

wake-up event that can activate the power-up request (PWUREQ).

SUSP

126

INTS

Suspend Power. Power Supply On control signal.

PC87351 데이터시트(PDF) 23 Page - National Semiconductor (TI)

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