PC87351 datasheet(5/86 Pages) NSC

5 / 86 page

Datasheet Revision Record (Continued)

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Keyboard Data Shift Register

Description modiﬁed

Section 3.4.6

Mouse Data Shift Register

Description modiﬁed

Section 3.4.7

Ports with fewer than 8 bits

Implementation description

Chapter 4

Interrupt Assertion and Handling

Bit nomenclature modiﬁed

Section 4.3

GPIO Pin Conﬁguration Access Register Bit nomenclature and descriptions changed

Section 4.4.1

GPIO Data Out Register

Bitmap and Reset values added

Section 4.4.3

GPIO Data In Register

Bitmap and Reset values added

Section 4.4.4

GPIO Interrupt Enable Register

Bitmap and Reset values added

Section 4.4.5

GPIO Status Register

Bitmap and Reset values added

Section 4.4.6

Functional Description

Corrected and enhanced

Section 5.2

Fan Control Duty Cycle Register

Bits 7-0

00h: PWM output is continuously low

01h-FEh: PWM output is high for [Duty Cycle Value] clock

cycles and low for [256-Duty Cycle Value] clock cycles

FFh: PWM output is continuously high

Section 5.3.3

Device Speciﬁcations

Timing diagrams drawn more precisely

Chapter 11

VBAT Battery Supply Current

Conditions and Max modiﬁed

Section 11.1.4

Host Interface I/O Cycle Timing

tRDYA, tRDYl and tRWl added to table; footnote 2 added

to table; IOCHRDY timing diagram added

Section 11.2.3

Serial IRQ Timing

Output timing diagram modiﬁed

Section 11.2.6

Item

Topic

Change/Correction

Location

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