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STGAP1S 데이터시트(PDF) 55 Page - STMicroelectronics |
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STGAP1S 데이터시트(HTML) 55 Page - STMicroelectronics |
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55 / 67 page ![]() DocID027190 Rev 3 55/67 STGAP1S Programming manual 67 9.2.4 CFG4 register (isolated side) The CFG4 register has the structure of Table 37. The OVLO_EN bit enables the OVLO protection on the VH and VL power supply according to Table 38. The UVLOlatch bit sets if the UVLO is latched or not (refer to Section 7.4 on page 29 for details). Table 36. 2-level turn-off time value 2LTOtime [3 ... 0] 2-level turn-off time value [µs] 0000 Disabled 0001 0.75 0010 1.00 0011 1.50 0100 2.00 0101 2.50 0110 3.00 0111 3.50 1000 3.75 1001 4.00 1010 4.25 1011 4.50 1100 4.75 1101 5.00 1110 5.25 1111 5.50 Table 37. CFG4 register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OVLO_EN UVLOlatch VLONth VHONth Default/reset 0 0 00 00 Table 38. VH and VL supply voltages OVLO enable OVLO_EN OVLO supply voltage enable 0 Disabled 1 Enabled |
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