STGAP1S datasheet(23/67 Pages) STMICROELECTRONICS

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STGAP1S

Logic supply management

6.2

High voltage section voltage regulator

The device integrates in the high voltage section a linear voltage regulator that generates

the 3.3 V logic core supply voltage from an external supply voltage connected to the VH pin.

Figure 4. High voltage section 3.3 V voltage regulator

If the voltage at the VREGISO pin goes below the minimum operating threshold which

causes the logic reset, the REG_ERR bit in the STATUS1 register is set high.

6.3

Power-up, power-down and “safe state”

The following conditions define the device's “safe state”:



GOFF = ON state



GON = high impedance



CLAMP = ON state (if CLAMP < 'GNDISO + VCLAMPth')



DESAT = GNDISO (internal switch on and current generator off)

Such conditions are guaranteed at power-up of the isolated side (also for VH < VHon

and VL > VLon) and during the whole device power-down phase (also for VH < VHoff

and VL > VLoff), whatever the value of the input pins.

The device integrates a structure which clamps the driver output to a voltage smaller than

SafeClp when the VH voltage is not high enough to actively turn the Goff N-channel

MOSFET on.

If the VH positive supply pin is floating the GOFF pin is clamped to a voltage smaller than

SafeClp.

After power-up of the isolated side the REGERRR status flag is latched and the device is

forced in “safe state”. See Section 7.11 on page 35 for indication on how the failure flags

can be released.

After power-up of the low voltage side the REGERRL and UVLOD status flags are latched

and the device is forced in “safe state”. See Section 7.11 for indication on how the failure

flags can be released.

The UVLOH flag is also forced high at the power-up of the low voltage side, but its value is

set to zero as soon as the isolated side power-up is completed.

VREGISO

LDO

Reg

4.7 µF

100 nF

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