SPC564A80L7 datasheet(75/157 Pages) STMICROELECTRONICS

75 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Pinout and signal description

Doc ID 15399 Rev 9

75/157

RD_WR

EBI

RD_WR indicates whether the current transaction is a read

access or a write access.

EBI

TA is asserted to indicate that the slave has received the data

(and completed the access) for a write cycle, or returned data

for a read cycle. If the transaction is a burst read, TA is asserted

for each one of the transaction beats. For write transactions, TA

is only asserted once at access completion, even if more than

one write data beat is transferred.

EBI

The Transfer Start signal (TS) is asserted by the SPC564A80 to

indicate the start of a transfer.

WE[2:3]

EBI

Write enables are used to enable program operations to a

particular memory. WE[2:3] are only asserted for write

accesses

WE[0:3]/BE[0:3]

EBI

Write enables are used to enable program operations to a

particular memory. These signals can also be used as byte

enables for read and write operation by setting the WEBS bit in

the appropriate EBI Base Register (EBI_BRn). WE[0:3] are

only asserted for write accesses. BE[0:3] are asserted for both

read and write accesses

eMIOS[0:23]

eMIOS

eMIOS I/O channels

AN[0:39]

eQADC

Single-ended analog inputs for analog-to-digital converter

FCK

eQADC

eQADC free running clock for eQADC SSI.

MA[0:2]

eQADC

These three control bits are output to enable the selection for

an external Analog Mux for expansion channels.

REFBYPC

eQADC

Bypass capacitor input

SDI

eQADC

Serial data in

SDO

eQADC

Serial data out

SDS

eQADC

Serial data select

VRH

eQADC

Voltage reference high input

VRL

eQADC

Voltage reference low input

SCI_A_RX

SCI_B_RX

SCI_C_RX

eSCI_A - eSCI_C

eSCI receive

SCI_A_TX

SCI_B_TX

SCI_C_TX

eSCI_A - eSCI_C

eSCI transmit

ETPU_A[0:31]

eTPU

eTPU I/O channel

Table 6.

Signal details (continued)

Signal

Module or Function

Description

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