SPC564A80L7 datasheet(17/157 Pages) STMICROELECTRONICS

17 / 157 page

SPC564A74L7, SPC564A80B4, SPC564A80L7

Introduction

Doc ID 15399 Rev 9

17/157

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The reset controller performs reset monitoring of internal and external reset sources, and

drives the RSTOUT pin. Communication between the SIU and the e200z4 CPU core is via

the crossbar switch. The SIU provides the following features:

●

System configuration

–

MCU reset configuration via external pins

–

Pad configuration control for each pad

–

Pad configuration control for virtual I/O via DSPI serialization

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System reset monitoring and generation

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Power-on reset support

–

Reset status register provides last reset source to software

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Glitch detection on reset input

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Software controlled reset assertion

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External interrupt

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Rising or falling edge event detection

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Programmable digital filter for glitch rejection

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Critical Interrupt request

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Non-Maskable Interrupt request

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GPIO

–

Centralized control of I/O and bus pins

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Virtual GPIO via DSPI serialization (requires external deserialization device)

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Dedicated input and output registers for setting each GPIO and Virtual GPIO pin

●

Internal multiplexing

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Allows serial and parallel chaining of DSPIs

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Allows flexible selection of eQADC trigger inputs

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Allows selection of interrupt requests between external pins and DSPI

1.5.8

Flash memory

The SPC564A80 provides up to 4 MB of programmable, non-volatile, flash memory. The

non-volatile memory (NVM) can be used to store instructions or data, or both. The flash

module includes a Fetch Accelerator that optimizes the performance of the flash array to

match the CPU architecture. The flash module interfaces the system bus to a dedicated

flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it

supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data

interfaces to flash memory. The module contains a prefetch controller which prefetches

sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait

responses.

The flash memory provides the following features:

●

Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte,

halfword, word and doubleword reads are supported. Only aligned word and

doubleword writes are supported.

●

Fetch Accelerator

–

Architected to optimize the performance of the flash

–

Configurable read buffering and line prefetch support

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