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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7FOXU0 데이터시트(PDF) 107 Page - STMicroelectronics |
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ST7FOXU0 데이터시트(HTML) 107 Page - STMicroelectronics |
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107 / 123 page  ST7FOXU0 Electrical characteristics 107/123 Figure 40. RESET pin protection when LVD is disabled 1. The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 12.9.1 on page 105. Otherwise the reset will not be taken into account internally. Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in Section Table 40. on page 94. 2. Please refer to Section 11.2.1 on page 89 for more details on illegal opcode reset conditions. 0.01 µF EXTERNAL RESET CIRCUIT USER Required ST72XXX PULSE GENERATOR Filter RON VDD INTERNAL RESET WATCHDOG ILLEGAL OPCODE |
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