ST7MC1K2 datasheet(324/371 Pages) STMICROELECTRONICS

324 / 371 page

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Product(s)

- Obsolete

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Electrical characteristics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

324/371

Figure 138. PLL and clock detector signal start up sequence

Lock does not go low without resetting the PLLEN bit.

Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of tlock must have

elapsed.

2 clock cycles are missing after CKSEL = 1.

CKSEL bit must be set before enabling the CSS interrupt (CSSIE

= 1).

12.6

Memory characteristics

12.6.1

RAM and hardware registers

OSC1

PLLEN

PLL CLOCK

LOCK

fCLK

tlock

CSSD

CSSIE(4)

INTERRUPT

tsetup

thold

16 MHz

fVCO =6 MHz

OSCI (or OSCIN clock)

PLL clock

(1)

CKSEL(2)

(3)

(PLL and CKD)

(or OSCIN)

Table 203.

RAM and hardware registers

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VRM

Data retention mode(1)

Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in

hardware registers (only in Halt mode). Not tested in production.

Halt mode (or reset)

1.6

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2 데이터시트(PDF) 324 Page - STMicroelectronics

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