ST7MC1K2 datasheet(328/371 Pages) STMICROELECTRONICS

328 / 371 page

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Electrical characteristics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

328/371

Static and dynamic latch-up

●

LU: 3 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

●

DLU: Electro-static discharges (one positive then one negative test) are applied to

each pin of three samples when the micro is running to assess the latch-up

performance in dynamic mode. Power supplies are set to the typical values, the

oscillator is connected as near as possible to the pins of the micro and the component

is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3

standards. For more details, refer to the application note AN1181.

Table 208.

Electrical sensitivities

Symbol

Parameter

Conditions

Class(1)

Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B

Class strictly covers all the JEDEC criteria (international standard).

Static latch-up class

TA =+25°C

TA = +125°C

DLU

Dynamic latch-up class

VDD = 5.5V, fOSC = 4 MHz,

TA =+25°C

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ST7MC1K2 데이터시트(PDF) 328 Page - STMicroelectronics