ST7MC1K2 datasheet(329/371 Pages) STMICROELECTRONICS

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Electrical characteristics

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12.8

I/O port pin characteristics

12.8.1

General characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 209.

General characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

CMOS ports

0.3 x VDD

VIH

Input high level voltage

0.7 x VDD

Vhys

Schmitt trigger voltage hysteresis(1)

VIL

Input low level voltage

G and H ports

0.8

VIH

Input high level voltage

2.8

Vhys

Schmitt trigger voltage hysteresis(1)

400

IINJ(PIN)

(2)

Injected current on an I/O

VDD =5V

+5/-2

ΣI

INJ(PIN)

(2) Total injected current (sum of all I/O

and control pins)

± 25

Input leakage current

VSS < VIN < VDD

±1

µA

Static current consumption induced by

each floating input pin(3)

Floating input mode

200

RPU

Weak pull-up equivalent resistor(4)

VIN =VSS

250

Ω

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time(5)

CL = 50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time(5)

tw(IT)in

External interrupt pulse time(6)

1tCPU

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS. Refer to Section 12.2.2: Current characteristics on page 314 for more

details.

Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 139). Static peak current value taken at a fixed VIN value,

based on design simulation and technology characteristics, not tested in production. This value depends on VDD and

temperature values.

The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in

Figure 140). This data is based on characterization results, tested in production at VDD max.

Data based on characterization results, not tested in production.

To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

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