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ST7MC1K2 데이터시트(PDF) 332 Page - STMicroelectronics

부품명 ST7MC1K2
상세설명  Clock, reset and supply management
PDF  371 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7MC1K2 데이터시트(HTML) 332 Page - STMicroelectronics

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Electrical characteristics
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
332/371
Figure 144. Typical VDD -VOH at VDD =5V
12.9
Control pin characteristics
12.9.1
Asynchronous RESET pin
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
-8
-6
-4
-2
0
Iio [mA]
1
2
3
4
5
6
Vdd-Voh [V] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
Table 211.
Asynchronous RESET pin
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage(1)
0.3xVDD
V
VIH
Input high level voltage(1)
0.7xVDD
Vhys
Schmitt trigger voltage hysteresis(2)
1
VOL
Output low level voltage(3)
VDD =5V
IIO = +5mA
0.5
1.2
IIO = +2mA
0.2
0.5
IIO
Driving current on RESET pin
2
mA
RON
Weak pull-up equivalent resistor
VIN =VSS, VDD = 5V
50
80
150
k
Ω
tw(RSTL)out
Generated reset pulse duration
Internal reset sources
30
µs
th(RSTL)in
External reset pulse hold time(4)
2.5
tg(RSTL)in
Filtered glitch duration(5)
450
ns
1.
Data based on characterization results, not tested in production.
2.
Hysteresis voltage between Schmitt trigger switching levels.
3.
The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2: Current characteristics
on page 314 and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
4.
To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
5.
The reset network protects the device against parasitic resets.
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