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ST10F296 데이터시트(PDF) 226 Page - STMicroelectronics

부품명 ST10F296
상세설명  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F296 데이터시트(HTML) 226 Page - STMicroelectronics

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System reset
ST10F296E
226/346
Figure 82.
Synchronous long hardware reset (EA = 0)
1.
If RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation) during the reset condition (
RSTIN low),
an asynchronous reset is entered immediately.
2.
The minimum RSTIN low pulse duration must be longer than 500 ns, to guarantee the pulse is not masked by the internal
filter (see Section 21.1: Idle mode on page 240).
3.
Three to eight TCL depending on clock source selection.
20.4
Software reset
A software reset sequence can be triggered at any time by the protected SRST (software
reset) instruction. This instruction can be executed within a program, for example: On a
hardware trap that reveals system failure or to leave bootstrap loader mode.
On execution of the SRST instruction, the internal reset sequence is started. The
microcontroller behavior is the same as for a synchronous short reset, except that only bits
P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bits
P0.7...P0.2 are cleared (written at 1).
A software reset is always taken as synchronous. There is no influence on software reset
behavior with RPD status. If a bidirectional reset is selected, a software reset event pulls the
RSTIN pin low. This occurs only if RPD is high. If RPD is low, the RSTIN pin is not pulled low
even though a bidirectional reset is selected.
See Figure 83 and Figure 84 which shows unidirectional software reset timing. See
Figure 85, Figure 86, and Figure 87 for bidirectional software reset timing.
P0[15:13]
Not transparent
RSTF
P0[12:2]
Transparent
Not t.
P0[1:0]
Not t.
Not transparent
RST
1024+8 TCL
3..8 TCL(3)
(1) V
RPD > 2.5 V asynchronous reset not entered
200 mA discharge
RPD
RSTOUT
At this time RSTF is sampled low
so it is a long reset
(after filter)
RSTIN
1024+8 TCL
4 TCL(2) 12 TCL
≤500 ns
≥ 50 ns
≤500 ns
≥ 50 ns
≤500 ns
≥ 50 ns
ALE
8 TCL
Not t.
Transparent
3..4 TCL
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