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ST10F296 데이터시트(PDF) 227 Page - STMicroelectronics

부품명 ST10F296
상세설명  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F296 데이터시트(HTML) 227 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
ST10F296E
System reset
227/346
20.5
Watchdog timer reset
When the watchdog timer is not disabled during initialization, or if it is not serviced regularly
during program execution, it overflows and triggers the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if the bus cycle does not use READY, or if READY is sampled active (low) after the
programmed wait states.
When READY is sampled inactive (high) after the programmed wait states, the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(written at 1).
A watchdog reset is always taken as synchronous. There is no influence on watchdog reset
behavior with RPD status. If a bidirectional reset is selected, a watchdog reset event pulls
the RSTIN pin low. This occurs only if RPD is high. If RPD is low, the RSTIN pin is not pulled
low even though a bidirectional reset is selected.
See Figure 83 and Figure 84 which shows unidirectional software reset timing. See
Figure 85, Figure 86, and Figure 87 for bidirectional software reset timing.
Figure 83.
Software/watchdog timer unidirectional reset (EA = 1)
P0[7:2]
Not transparent
P0[12:8]
Transparent
Not t.
P0[1:0]
Not t.
not transparent
RST
1024 TCL
RSTOUT
RSTIN
IBUS-CS
7 TCL
P0[15:13]
Not transparent
FLARST
≤1 ms
(internal)
≤2 TCL
Obsolete
Product(s)
- Obsolete
Product(s)



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