ST10F296 datasheet(242/346 Pages) STMICROELECTRONICS

242 / 346 page

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Power reduction modes

ST10F296E

242/346

Figure 93.

External RC circuit on the RPD pin

To exit power-down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be

asserted for at least 40 ns.

This signal enables the internal oscillator and PLL circuitry. It also turns on the weak pull-

down (see Figure 94).

The discharge of the external capacitor provides a delay that allows the oscillator and PLL

circuits to stabilize before the internal CPU and peripheral clocks are enabled. When the

RPD voltage drops below the threshold voltage (about 2.5 V), the Schmitt trigger clears Q2

flip-flop, the CPU and peripheral clocks are enabled, and the device resumes code

execution.

If the interrupt is enabled (CCxIE bit = 1 in the CCxIC register) before entering power-down

mode, the device executes the interrupt service routine and resumes execution after the

PWRDN instruction (see note below).

If the interrupt is disabled, the device executes the instruction following the PWRDN

instruction and the interrupt request flag remains set (using the CCxIR bit in the CCxIC

Note:

Due to the internal pipeline, the instruction that follows the PWRDN instruction is executed

before the CPU performs a call of the interrupt service routine when exiting power-down

mode.

RPD

VDD

220 k

Ω minimum

1 µF typical

ST10F296E

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 데이터시트(PDF) 242 Page - STMicroelectronics