ST10F296 datasheet(240/346 Pages) STMICROELECTRONICS

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Power reduction modes

ST10F296E

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Power reduction modes

Three different power reduction modes with different levels of power saving have been

implemented in the ST10F296E. In idle mode, the CPU is stopped, but, peripherals still

operate. In power-down mode, both the CPU and peripherals are stopped. In stand-by

mode, the main power supply (VDD) can be turned off while a portion of the internal RAM

remains powered via the dedicated power pin, VSTBY.

Idle and power-down modes are software activated by a protected instruction and are

terminated in different ways as described in the following sections.

Stand-by mode is entered by removing VDD and holding the MCU under reset state.

21.1

Idle mode

Idle mode is entered by running the IDLE protected instruction. CPU operation is stopped

but, the peripherals continue to run.

Idle mode is terminated by any interrupt request. Whether the interrupt is serviced or not,

the instruction following the IDLE instruction, is executed after a return from the interrupt

instruction (RETI). The CPU then resumes normal programming.

Note that a PEC transfer keeps the CPU in idle mode. If the PEC transfer does not succeed,

idle mode is terminated. The watchdog timer must be properly programmed to avoid any

disturbance during idle mode.

21.2

Power-down mode

Power-down mode starts by running the PWRDN protected instruction. The internal clock is

stopped, all MCU parts, including the watchdog timer, are put on hold. The only exception is

the RTC, if it has been opportunely programmed, and consequently, the main oscillator

circuits.

When the RTC module is used, and the device is in power-down mode, a reference clock is

needed. Accordingly, the main oscillator is kept running (XTAL1/XTAL2 pins). In this way, the

RTC continues counting using the main oscillator clock signal as a reference.

There are two different operating power-down modes:

●

Protected mode

●

Interruptible mode

The internal RAM contents can be preserved through the voltage that is supplied via the

VDD pins. To verify RAM integrity, some dedicated patterns may be written before entering

power-down mode which must be checked after power-down is resumed.

Power-down mode is entered by executing the PWRDN instruction. Before entering it, the

VREGOFF bit in the XMISC register must be set. In this way, as soon as the PWRDN

command is executed, the main voltage regulator is turned off, and only the low power

voltage regulator remains active.

Note:

Leaving the main voltage regulator active during power-down may lead to unexpected

behavior (example, CPU wake-up). Power consumption is also higher than that specified in

Table 163: DC characteristics on page 295.

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