ST10F296 datasheet(281/346 Pages) STMICROELECTRONICS

281 / 346 page

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7WRCFG(1)

Write configuration control (inverted copy of the WRC bit of the RP0H

0: WR and BHE pins retain their normal function.

1: WR and BHE pins behave as the WRL and WRH pins respectively

6CSCFG

Chip select configuration control

0: Latched chip select lines, CSx changes 1 TCL after rising edge of

ALE

1: Unlatched chip select lines, CSx changes with rising edge of ALE

PWDCFG

Power-down mode configuration control

0: Power-down mode can only be entered during PWRDN instruction

execution if NMI pin is low, otherwise, the instruction has no effect. To

exit power-down mode, an external reset must occur by asserting the

RSTIN pin.

1: Power-down mode can only be entered during PWRDN instruction

execution if all enabled fast external interrupt EXxIN pins are in their

inactive level. Exiting this mode can be done by asserting one enabled

EXxIN pin.

OWDDIS

Oscillator watchdog disable control

0: Oscillator watchdog (OWD) is enabled. If PLL is bypassed, the

OWD monitors XTAL1 activity. If there is no activity on XTAL1 for at

least 1 µs, the CPU clock is switched automatically to PLL’s base

frequency (250 Hz to 4 MHz).

1: OWD is disabled. If the PLL is bypassed, the CPU clock is always

driven by the XTAL1 signal. The PLL is turned off to reduce power

supply current.

BDRSTEN

Bidirectional reset enable

0: RSTIN pin is an input pin only. SW reset or WDT reset have no

effect on this pin.

1: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024

TCL during reset sequence.

XPEN

XBus peripheral enable bit

0: Access to the on-chip XPeripherals and their functions are disabled.

1: The on-chip XPeripherals are enabled and can be accessed.

VISIBLE

Visible mode control

0: Access to the XBus peripherals is made internally.

1: Access to the XBus peripherals is made visible on the external pins.

XPERSHARE

XBus peripheral share mode control

0: External access to the XBus peripherals is disabled.

1: XRAM1 and XRAM2 are accessible via the external bus during hold

mode. External access to other XBus peripherals is not guaranteed in

terms of AC timings.

Bits are set directly or indirectly during the rest sequence according to Port 0 and the EA pin configuration.

Table 150.

SYSCON register description (continued)

Bit

Bit name

Function

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ST10F296 데이터시트(PDF) 281 Page - STMicroelectronics

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