ST10F296 datasheet(298/346 Pages) STMICROELECTRONICS

298 / 346 page

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Electrical characteristics

ST10F296E

298/346

Figure 96.

Port 2 test mode structure

For the complete structure of Port 2, see Figure 37 in Section 13.4

The power supply current is a function of the operating frequency (fCPU is expressed in MHz). This

dependency is illustrated in Figure 97 below. This parameter is tested at VDDmax and at maximum CPU

clock frequency with all outputs disconnected, all inputs at VIL or VIH, and RSTIN pin at VIH1min: This

implies that I/O current is not considered. The device does the following:

- Fetches code from IRAM and XRAM1, read and write accesses both XRAM modules

- Enables watchdog timer and services it regularly

- RTC runs with main oscillator clock as reference, generating a tick interrupt every 192 clock cycles

- Four XPWM channels run (wave periods: 2, 2.5, 3, and 4 CPU clock cycles): No output toggling

- Five general purpose timers run in timer mode with prescaler equal to 8 (T2, T3, T4, T5, and T6)

- ADC is in auto scan continuous conversion mode on all 16 channels of Port 5

- All interrupts generated by XPWM, RTC, timers and ADC are not serviced

10. The idle mode supply current is a function of the operating frequency (fCPU is expressed in MHz). This

dependency is illustrated in Figure 97 below. These parameters are tested at maximum CPU clock with all

outputs disconnected, all inputs at VIL or VIH, and the RSTIN pin at VIH1min.

11. Testing of this parameter includes leakage currents. All inputs (including pins configured as inputs) are at 0

to 0.1 V or at VDD - 0.1 V to VDD, VAREF = 0 V, all outputs (including pins configured as outputs) are

disconnected. The main voltage regulator is assumed to be off. If this is not the case, an additional 1 mA

must be assumed.

Input

latch

Clock

P2.0

CC0IO

Output

buffer

Test mode

Alternate data input

Fast external interrupt input

Flash sense amplifier

and column decoder

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ST10F296 데이터시트(PDF) 298 Page - STMicroelectronics

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