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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72344S2 데이터시트(PDF) 62 Page - STMicroelectronics |
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ST72344S2 데이터시트(HTML) 62 Page - STMicroelectronics |
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62 / 247 page  Interrupts ST72344xx, ST2345xx 62/247 Doc ID 12321 Rev 6 Bits 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: ● ei0 (port A3, port E1) ● ei1 (port F2..0) These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 2 = IPA Interrupt polarity for ports A3 and E1 This bit is used to invert the sensitivity of the port A3 and E1 external interrupts. It can be set and cleared by software only when I1 and I0 of the CC register are both set to 1 (level 3). 0: No sensitivity inversion 1: Sensitivity inversion Bits 1:0 = Reserved, must always be kept cleared. Table 20. External interrupt sensitivity (ei0) IS21 IS20 Sensitivity IPA bit =0 IPA bit =1 0 0 Falling edge & low level Rising edge & high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge Table 21. External interrupt sensitivity (ei1) IS21 IS20 Sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge |
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