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ST72344S2 데이터시트(PDF) 92 Page - STMicroelectronics |
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ST72344S2 데이터시트(HTML) 92 Page - STMicroelectronics |
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92 / 247 page ![]() On-chip peripherals ST72344xx, ST2345xx 92/247 Doc ID 12321 Rev 6 The beep output signal is available in Active-halt mode but has to be disabled to reduce the consumption. Table 43. Beep control BC1 BC0 Beep mode with fOSC2 = 8 MHz 00 Off 01 ~2-kHz Output beep signal ~50% duty cycle 10 ~1-kHz 1 1 ~500-Hz Table 44. Main clock controller register map and reset values Address (Hex.) Register label 76 5 4 3 2 1 0 002Bh SICSR Reset value 0 AVDIE 0 AVDF 0 LVDRF x LOCKED 00 0 WDGRF x 002Ch MCCSR Reset value MCO 0 CP1 0 CP0 0 SMS 0 TB1 0 TB0 0 OIE 0 OIF 0 002Dh MCCBCR Reset value 0 0 0 0 0 0 BC1 0 BC0 0 |
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