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ST72344S2 데이터시트(PDF) 84 Page - STMicroelectronics

부품명 ST72344S2
상세설명  SCI asynchronous serial interface
PDF  247 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72344S2 데이터시트(HTML) 84 Page - STMicroelectronics

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On-chip peripherals
ST72344xx, ST2345xx
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Doc ID 12321 Rev 6
Note:
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
●
Watchdog reset on Halt option
If the watchdog is activated and the watchdog reset on halt option is selected, then the
HALT instruction will generate a Reset.
11.1.4
Using Halt mode with the WDG
If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
11.1.5
How to program the watchdog timeout
Figure 38 shows the linear relationship between the 6-bit value to be loaded in the watchdog
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in Figure 39.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 38.
Approximate timeout duration
Watchdog timeout (ms) @ 8 MHz fOSC2
3F
00
38
128
1.5
65
30
28
20
18
10
08
50
34
18
82
98
114



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