ST72344S2 datasheet(126/247 Pages) STMICROELECTRONICS

126 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

126/247

Doc ID 12321 Rev 6

Bit 4 = MSTR Master Mode

This bit is set and cleared by software. It is also cleared by hardware when, in master

mode, SS =0 (see Master mode fault (MODF)).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL Clock Polarity

This bit is set and cleared by software. This bit determines the idle state of the serial

Clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note:

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

Bit 2 = CPHA Clock Phase

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note:

The slave must have the same CPOL and CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial clock frequency

These bits are set and cleared by software. Used with the SPR2 bit, they select the

baud rate of the SPI serial clock SCK output by the SPI in master mode.

Note:

These 2 bits have no effect in slave mode.

SPI control/status register (SPICSR)

Reset value: 0000 0000 (00h)

Table 54.

SPI master mode SCK frequency

Serial clock

SPR2

SPR1

SPR0

fCPU/4

fCPU/8

fCPU/16

fCPU/32

fCPU/64

fCPU/128

SPIF

WCOL

OVR

MODF

SOD

SSM

SSI

Read-only

Reserved

Read/Write

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