ST72344S2 datasheet(142/247 Pages) STMICROELECTRONICS

142 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

142/247

Doc ID 12321 Rev 6

11.5.6

Interrupts

The SCI interrupt events are connected to the same interrupt vector.

These events generate an interrupt if the corresponding Enable Control Bit is set and the

interrupt mask in the CC register is reset (RIM instruction).

11.5.7

Status register (SCISR)

Reset value: 1100 0000 (C0h)

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the TDR register has been transferred

into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register.

It is cleared by a software sequence (an access to the SCISR register followed by a

write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note:

Data is not transferred to the shift register until the TDRE bit is cleared.

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a frame containing Data is complete.

An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register followed by a write to the SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note:

TC is not set after the transmission of a Preamble or a Break.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the RDR register has been transferred

to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is

Table 58.

Interrupt events

Interrupt event

Event flag

Enable control

bit

Exit from

Wait

Exit from

Halt

Transmit data register empty

TDRE

TIE

Yes

Transmission complete

TCIE

Received data ready to be read

RDRF

RIE

Overrun error detected

Idle line detected

IDLE

ILIE

Parity error

PIE

TDRE

RDRF

IDLE

Read-only

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