AS4C64M8D2 datasheet(29/59 Pages) ALSC

29 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

NOTE 9:tIS and tIH (input setup and hold) derating

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet

tIS(base) and tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) =

tIS(base) + ΔtIS

For slew rates in between the values listed in Tables 27, the derating values may obtained by linear

interpolation.These values are typically not subject to production test. They are verified by design and

characterization

Table 27. Derating values for DDR2-667, DDR2-800

△tIS and △tIH Derating Values for DDR2-667, DDR2-800

CK,CK# Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

△tIS

△tIH

△tIS

△tIH

△tIS

△tIH

Units

Notes

Command/

Address Slew rate

(V/ns)

4.0

+150

+94

+180

+124

+210

+154

3.5

+143

+89

+173

+119

+203

+149

3.0

+133

+83

+163

+113

+193

+143

2.5

+120

+75

+150

+105

+180

+135

2.0

+100

+45

+130

+75

+160

+105

1.5

+67

+21

+97

+51

+127

+81

1.0

+30

+60

0.9

-5

-14

+25

+16

+55

+46

0.8

-13

-31

+17

-1

+47

+29

0.7

-22

-54

-24

+38

0.6

-34

-83

-4

-53

+26

-23

0.5

-60

-125

-30

-95

-65

0.4

-100

-188

-70

-158

-40

-128

0.3

-168

-292

-138

-262

-108

-232

0.25

-200

-375

-170

-345

-140

-315

0.2

-325

-500

-295

-470

-265

-440

0.15

-517

-708

-487

-678

-457

-648

0.1

-1000

-1125

-970

-1095

-940

-1065

NOTE 10: The maximum limit for this parameter is not a device limit. The device will operate with a greater value

for this parameter, but system performance (bus turnaround) will degrade accordingly.

NOTE 11: MIN (tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as

provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).

NOTE 12:tQH = tHP – tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL). tQHS

accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-

channel variation of the output drivers.

NOTE 13: tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the

output drivers as well as output slew rate mismatch between DQS / DQS# and associated DQ in any given

cycle.

NOTE 14: tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.WR refers to the tWR parameter stored

in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.

tCK refers to the application clock period.

NOTE 15: The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In

case of clock frequency change during precharge power-down.

NOTE 16: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted

as 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.

AS4C64M8D2 데이터시트(PDF) 29 Page - Alliance Semiconductor Corporation

AS4C64M8D2 데이터시트(HTML) 29 Page - Alliance Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

데이터시트 다운로드

링크 URL