AS4C64M8D2 datasheet(42/59 Pages) ALSC

42 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Figure 26. Burst write followed by burst read:

RL=5 (AL=2, CL=3, WL=4, tWTR=2, BL=4)

CK#

CKE

NOP

Post CAS#

READ A

NOP

DQS

AL=2

DQS#

WL = RL-1 = 4

DQS#

DQS

CL=3

RL=5

>=tWTR

DNA0 DNA1 DNA2 DNA3

DOUT A0

NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + tWTR].

This tWTR is not a write recovery time (tWR) but the time required to transfer the 4 bit write data from the input buffer into

sense amplifiers in the array. tWTR is defined in the timing parameter table of this standard.

Write to Read = CL-1+BL/2+tWTR

Figure 27. Seamless burst write operation RL=5, WL=4, BL=4

CK#

CMD

Post CAS#

Write A

NOP

Post CAS#

Write B

NOP

DQS

DQS#

WL = RL-1 = 4

DQS#

DQS

DNA0 DNA1 DNA2 DNA3

DNB0 DNB1 DNB2 DNB3

NOTE : The seamless burst write operation is supported by enabling a write command every other clock for

BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or

different banks as long as the banks are activated.

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