AS4C64M8D2 datasheet(40/59 Pages) ALSC

40 / 59 page

AS4C64M8D2

Confidential

Rev. 1.0

Feb. /2014

Figure 22. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4

CK#

DQs

CMD

DQS

Post CAS#

READ A

NOP

Post CAS#

READ B

NOP

Dout A0

AL=2

DQS#

Dout A1

Dout A2

Dout A3 Dout B0

Dout B1 Dout B2

CL=3

RL=5

NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =

4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks

as long as the banks are activated.

Figure 23. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)

CK#

CMD

Read A

NOP

Read B

NOP

DQS

DQS#

DQs

NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write

command or Precharge command is prohibited.

NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst

interrupt timings are prohibited.

NOTE 4: Read burst interruption is allowed to any bank inside DRAM.

NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.

NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.

NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the

mode register and not the actual burst (which is shorter because of interrupt).

AS4C64M8D2 데이터시트(PDF) 40 Page - Alliance Semiconductor Corporation

AS4C64M8D2 데이터시트(HTML) 40 Page - Alliance Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

데이터시트 다운로드

링크 URL