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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SPEAR600 데이터시트(PDF) 72 Page - STMicroelectronics |
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SPEAR600 데이터시트(HTML) 72 Page - STMicroelectronics |
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72 / 97 page  Timing characteristics SPEAr600 72/97 Doc ID 16259 Rev 3 Note: 1 Tstable = Tclock direct max - (Tmax + Tmin) 2 For Tmax the maximum value is taken from the worst case and best case, while for Tmin the minimum value is taken from the worst case and best case. 3CLCP should be delayed by {Tmax + [Tclock direct max - (Tmax + Tmin)]/2} = 4.7915 ns 6.3.2 CLCD timing characteristics divided clock Figure 17. CLCD waveform with CLCP divided Figure 18. CLCD block diagram with CLCP divided Table 44. CLCD timings with CLCP divided Parameter Value Frequency Tclock divided max 12 ns 83.3 MHz Tclock divided max rise (Tr) 0.81 ns Tclock divided max (Tf) 0.87 ns Tmin -0.49 ns Tmax 2.38 ns Tstable 9.13 ns Tmin Tmax CLCP CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER Tclock Tr Tf Tstable Q Q SET CLR D t2 CLCP CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER CLCDCLK t1 Q Q SET CLR D t3 |
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