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SPEAR600 데이터시트(PDF) 77 Page - STMicroelectronics

부품명 SPEAR600
상세설명  Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface
PDF  97 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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SPEAR600 데이터시트(HTML) 77 Page - STMicroelectronics

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SPEAr600
Timing characteristics
Doc ID 16259 Rev 3
77/97
Figure 26.
Output address signal waveforms for 8-bit NAND Flash configuration
Figure 27.
In/out data address signal waveforms for 8-bit NAND Flash configuration
Table 48.
Timing characteristics for 8-bit NAND Flash configuration
Parameter
Min
Max
TCLE
-16.85 ns
-19.38 ns
TALE
-16.84 ns
-19.37 ns
TWE (s=1)(1)
1.
TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE,
respectively. Both are composed by the algebric sum of a fixed part (due to the internal delays of Spear)
and a programmable one in a FSMC register. The programmable one is equal to (s+1)*Thclk where
s=Tset. The values shown in the table are calculated using s=1
11.10 ns
13.04 ns
TRE (s=1)(1)
11.18 ns
13.05 ns
TIO (h=1)(2)
2.
TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on
the min or the max timing. It's composed by the algebric sum of a fixed part (due to the internal delays of
Spear) and a programmable one in a FSMC register. The programmable one is equal to h*Thclk where
h=Thiz. The values shown in the table are calculated using h=1.
3.
TREAD is the timing between the falling edge and the rising edge of NFRE. This value is fully
programmable and it's equal to
T(read) = (w+1)*T(hclk) >= T(re->io) + T(nfio->FFs)
where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal
delay (~9 ns).
3.43 ns
8.86 ns
NFALE
NFCE
NFWE
NFIO
Address
TALE
TWE
TIO
NFCE
NFWE
NFIO (out)
Data Out
TIO
NFIO (in)
NFRE
TRE -> IO
TWE
TRE
TREAD
TNFIO -> FFs
(3)



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