SPEAR600 datasheet(87/97 Pages) STMICROELECTRONICS

87 / 97 page

SPEAr600

Timing characteristics

Doc ID 16259 Rev 3

87/97

The Motorola SPI interface is a four-wire interface where SSP_SS signal behaves as a slave

select.

The main feature of the Motorola SPI format is that the inactive state and phase of the

output clock signal are programmable through the CPOL (clock polarity) and CPHA (clock

phase) parameters inside an IP control register.

●

CPOL, clock polarity:

When CPOL clock polarity control parameter is low, it produces a steady state low

value on the output clock pin. If this parameter is high, a steady state high value is

placed on the output clock pin when data is not being transferred.

●

CPHA, clock phase:

The CPHA clock phase control parameter selects the clock edge that captures data

and allows it to change state. When CPHA is low, data is captured on the first clock

edge transition after slave selection and is changed on the second clock edge

transition. If the CPHA clock phase control parameter is high, data is captured on the

second clock edge transition after the slave selection and is changed on the first clock

edge transition.

6.8.1

SPI master mode timings (CPHA = 0)

Table 57.

Timing requirements for SPI mode on MISO pad [CPHA = 0]

parameters

CPOL

SPI1

SPI2

SPI3

unit

Setup time, MISO (input)

valid before SSP_SCLK

(output) rising edge

9.563

10.759

10.357

Setup time, MISO (input)

valid before SSP_SCLK

(output) falling edge

9.632

10.804

10.427

Hold time, MISO (input)

valid after SSP_SCLK

(output) rising edge

-8.849

-10.112

-9.753

Hold time, MISO (input)

valid after SSP_SCLK

(output) falling edge

-8.956

-10.149

-9.785

Table 58.

Timing requirements for SPI mode on MOSI pad [CPHA = 0]

parameters

CPOL

SPI1

SPI2

SPI3

unit

Delay time, SSP_SCLK

(output) falling edge to

MOSI (output) transition

-0.675

-1.141

-1.638

Delay time, SSP_SCLK

(output) rising edge to

MOSI (output) transition

-0.607

-1.097

-1.568

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