HT67F488 datasheet(18/171 Pages) HOLTEK

18 / 171 page

Rev. 1.60

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HT67F488/HT67F489

TinyPowerTM A/D Flash MCU with LCD & EEPROM

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed

totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound

withinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhancedperformance.

Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstruction

executionareoverlapped,henceinstructionsareeffectivelyexecutedinoneortwocyclesformost

ofthestandardorextendedinstructionsrespectively.Theexceptionstothisarebranchorcall

instructionswhichneedonemorecycle.An8-bitwideALUisusedinpracticallyallinstructionset

operations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,

branchdecisions,etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulator

andtheALU.CertaininternalregistersareimplementedintheDataMemoryandcanbedirectly

orindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditional

architecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovidea

functionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthe

devicessuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeitheraHIRC,HXT,LXTorLIRCoscillatorissubdivided

intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincremented

atthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.Theremaining

T2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clock

cycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplace

inconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat

instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions

wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich

casetheinstructionwilltakeonemoreinstructioncycletoexecute.

Fe tc h In st . ( PC )

Ex ec ut e In st . (P C- 1)

Fe tc h In st . (P C+ 1)

Ex ec ut e In st . (P C)

Fe tc h In st . (P C+ 2)

Ex ec ut e In st . (P C+ 1)

PC +1

PC +2

f SY S

(S yst em C lo ck)

P has e Cl o ck T1

Pr ogr am C oun te r

P has e Cl o ck T2

P has e Cl o ck T3

P has e Cl o ck T4

Pi pe lin in g

System Clocking and Pipelining

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