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WM8232 데이터시트(PDF) 35 Page - Cirrus Logic

부품명 WM8232
상세설명  105MSPS 3-Channel AFE with Sensor
PDF  141 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8232 데이터시트(HTML) 35 Page - Cirrus Logic

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WM8232
Rev 4.6
35
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R176 (B0h)
– R177 (B1h)
5:0
DEL_PCK*[1:0]
00
control delay for pulse output
00 = 0nsec, 01 = 1nsec, 10 = 2nsec, 11 = 3nsec
R135 (81h)
– R146 (92h)
5:0
CLK*_RISE[5:0]
CLK* rise edge (0 to 59)
5:0
CLK*_FALL[5:0]
CLK* fall edge (0 to 59)
TG MASTER MODE OPERATION
In master mode, line length is defined by LLENGTH register.
master
L=LLENGTH[14:0]
Datatrig(Internal)
Datatrig
(LVDS/CMOS output)
TGCK
TGEN(Serial I/F)
Pixel counter
TGSYNC(Output)
tTRIGD
pixcnt=0
pixcnt=0
pixcnt=0
POn(Internal)
CLKn(TG pulse out)
FLAGPIX=P1
TPn=P1
TPm=P2
tPCKD
PO_ Flag
(LVDS/CMOS out)
tTRIGD
VSMP
TGCK
2*tPER/60
VSMP
Figure 22 Master Mode Pixel Counter and Line Start Timing
TG SLAVE MODE OPERATION
In slave mode, line length depends on TGSYNC input. The pixel counter is reset by TGSYNC input.
slave
TGSYNC(Input)
32767
0
tTRIGD
TGCK
TGEN(Serial I/F)
Linestart(Internal)
Pixel counter
tCOUNTD
pixcnt=0
pixcnt=0
pixcnt=0
Q=OFFSET[3:0]
FLAGPIX=P1
tSCKSY
TGCK
TGSYNC
tSYH
Flag(Internal)
Flag
(LVDS/CMOS out)
TPn=P1
POn(Internal)
TPm=P2
CLKn(TG pulse out)
tPCKD
PO_Flag
(LVDS/CMOS out)
tTRIGD
VSMP
2*tPER/60
VSMP
tSYH
tSYL
Figure 23 Slave Mode Pixel Counter and Line Start Timing



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