PC87372 datasheet(26/144 Pages) NSC

26 / 144 page

2.0 Power, Reset and Clocks (Continued)

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Revision 1.2

Figure 2. Decoupling Capacitors Connection

2.2 RESET SOURCES AND TYPES

The PC87372 device has four reset sources:

• V

SB Power-Up Reset - activated when VSB3 is powered up.

• V

DD Power-Up Reset - activated when VDD3 is powered up.

• Hardware Reset - activated when the PCI_RESET input is asserted (low).

• Software Reset - triggered by SWRST bit in SIOCF1 register (see Section 3.7.2 on page 40); SWRST bit is set by the

host through the LPC interface.

Unless otherwise noted, reset references throughout the modules of the PC87372 devices default to the following resets:

For VSB3-powered functions (GPIO ports, SWC, Glue Functions and some Conﬁguration Control): VSB Power-Up re-

set (within the limitations described in Section 2.2.1).

For VDD3-powered functions (Legacy modules, LPC, on-chip Clock Generator, FSM and some Conﬁguration Control):

VDD Power-Up reset, Hardware Reset or Software Reset (within the limitations described in Sections 2.2.2, 2.2.3 and

2.2.4).

The following sections detail the sources and effects of the various PC87372 resets.

2.2.1

VSB Power-Up Reset

VSB Power-Up reset is generated by an internal circuit when VSB3 power is applied. The VSB Power-Up reset time (tIRST)

lasts either 17 cycles of the 32 KHz clock domain or until the PCI_RESET signal is de-asserted, whichever occurs first. Ex-

ternal devices must wait at least tIRST before accessing the PC87372 device.

Note that the 32 KHz clock domain starts toggling t32KW +t32KVAL after VSB3 power-up. This delay must be added to the 17

clock cycles (see Low-Frequency Clock Timing on page 132).

VSB Power-Up reset performs the actions listed below and all the actions performed by VDD Power-Up reset (see Section

2.2.2). Note that VDD3 must be active during VSB3 power-up for all VDD Power-Up reset actions to be performed:

• Resets all lock bits in configuration registers and SWC

• Loads default values to VDDLOAD bits in the GPIO configuration registers

• Loads default values to the V

SB3-powered bits in the configuration registers, SWC and GPIO

• Sets up the pull-up option and the default source for the V

SB3-powered multiplexed output pins

VDD3

PC87372

0.1

µF

0.1

µF

0.1

µF

0.1

µF

VSS

VDD3

VSS

10-47

µF

Main 3.3V

VSB3

VSS

VSB3

VSS

0.1

µF

0.1

µF

0.1

µF

110

107

10-47

µF

Standby 3.3V

µF

VCORF

VSB5

0.1

µF

Standby 5V

PC87372 데이터시트(PDF) 26 Page - National Semiconductor (TI)

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