PC87372 datasheet(41/144 Pages) NSC

41 / 144 page

3.0 Device Architecture and Configuration (Continued)

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Revision 1.2

3.7.3

SuperI/O Configuration 2 Register (SIOCF2)

Power Well: VSB3

Location:

Index 22h

Type:

R/W or RO

3.7.4

SuperI/O Configuration 6 Register (SIOCF6)

This register provides a fast way to disable one or more modules without having to access the Activate register of each (see

Section 3.3.1 on page 36).

Power Well: VDD3

Location:

Index 26h

Type:

Varies per bit

Bit

43210

Name

PMEPOL

PMETYPE

TACH2EN

TACH1EN

Reserved

GPIO03EN

Reset

00000

Bit

Description

PMEPOL (SIOPME Polarity). Selects the polarity of the SIOPME signal.

0: SIOPME is active low (default)

1: SIOPME is active high

PMETYPE (SIOPME Buffer Type). Selects the output buffer type of the SIOPME pin.

0: Output is open-drain and the pull-up resistor is enabled (default)

1: Output is push-pull (the pull-up resistor is disabled)

TACH2EN (FANTACH2 Multiplex Control). Selects the function connected to pin 112.

0: GPIOE07 port: GPIO (default)

1: FANTACH2: FSM

TACH1EN (FANTACH1 Multiplex Control). Selects the function connected to pin 111.

0: GPIOE06 port: GPIO (default)

1: FANTACH1: FSM

3-1

Reserved.

GPIO03EN (GPIOE10-GPIOE13 Multiplex Control). Selects the functions connected to pins 113-116.

0: 5V_DDCSDA, 5V_DDCSCL, 3V_DDCSDA, 3V_DDCSCL: Glue Functions (default)

1: GPIOE10-GPIOE13 ports: GPIO

Bit

43210

Name

LOCKFDS

General-Purpose

Scratch

Reserved

SERDIS

Reserved

PARPDIS

FDCDIS

Reset

00000

Bit

Type

Description

R/W1S LOCKFDS (Lock Fast Disable Configuration). When set to 1, this bit locks itself, SERDIS, PARPDIS

and FDCDIS bits in this register and GLOBEN bit in SIOCF1 register by disabling writing to all of these

bits. Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware reset).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-5

R/W

General-Purpose Scratch.

−

Reserved.

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