PC87372 datasheet(61/144 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.2

3.14.3 Fan Speed Monitor Configuration Register (FSMCF)

This register is reset to 00h.

Power Well: VDD3

Location:

Index F0h

Type:

Varies per bit

Bit

76543210

Name

LOCKFCF

Reserved

FANMON

_EN2

Reserved

FANMON

_EN1

Reserved

Reset

00000000

Bit

Type

Description

R/W1S LOCKFCF (Lock Fan Speed Configuration). When set to 1, this bit locks the bits of the FSMCF

by VDD3 Power-Up reset (or Hardware reset).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-5

−

Reserved.

R/W or

FANMON_EN2 (Fan Monitor Enable 2). When this bit is set to 1, the Fan Speed Monitor 2 is enabled

and the rate of pulses received at the FANTACH2 tachometer input is measured.

0: Disabled (default)

1: Enabled

3-2

−

Reserved.

R/W or

FANMON_EN1 (Fan Monitor Enable 1). When this bit is set to 1, the Fan Speed Monitor 1 is enabled

and the rate of pulses received at the FANTACH1 tachometer input is measured.

0: Disabled (default)

1: Enabled

−

Reserved.

PC87372 데이터시트(PDF) 61 Page - National Semiconductor (TI)

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