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WM8602SEDS/V 데이터시트(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8602SEDS/V 데이터시트(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 46 page ![]() Product Preview WM8602 w PP Rev 1.5 May 2004 9 AUDIO INTERFACE TIMING – MASTER MODE Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge tDL 10 ns DIN setup time to BCLK rising edge tDST 10 ns DIN hold time from BCLK rising edge tDHT 10 ns Table 4 Audio Interface Timing – Master Mode BCLK (Output) LRCLK (Output) t DL DIN t DHT t DST |
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