WM8602SEDSSLASHV datasheet(36/46 Pages) WOLFSON

36 / 46 page

WM8602

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PP Rev 1.5 May 2004

PWM OUTPUT CONFIGURATION

The PWM output format can be defined with the PWMCFG setting defined in Table 46.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

2:1

PWMCFG

[1:0]

PWM Output State when output disabled

or in standby mode:

01 = all PWM Outputs high

00 = all PWM Outputs low

10, 11 = high impedance

PWMPH

PWM Output Phase

0 = PWM outputs in phase

1 = PWM outputs phase shifted to each

other

R27 (1Bh)

PWM Output

Configuration

PWMCLK

PWM Output Clock

0 = disabled

1 = enabled

Table 46 PWM Output Configuration

OUTPUT CONFIGURATION

If required the WM8602 device can be disabled in a system by setting the TRI bit as defined in Table

47. Setting the TRI bit will set all output pins of the device to high impedance.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R28 (1Ch)

Output

Configuration

TRI

Output Pins Mode

0 = Normal

1 = High Impedance

Table 47 Output Configuration

STANDBY, OUTPUT DISABLE AND RESET MODES

STANDBY

Setting the STDBY register bit selects a low power mode, and immediately configures the output to

produce an output defined in Table 46 (PWMCFG). All trace of the previous input samples is

removed, but all control register settings are preserved.

OUTPUT DISABLE (OPDIS) PIN AND REGISTER (OPDISR)

The OPDIS pin is provided to immediately shutdown the outputs, primarily for their protection. This is

useful for short-circuit or thermal protection. The OPDIS pin can be configured in 2 modes:

•

Synchronous

•

Latched

In synchronous mode if OPDIS is high for longer than 100ns the outputs will be disabled. They will be

enabled again at the end of a processing frame when OPDIS goes low for longer than 100ns.

In latched mode if OPDIS is high for longer than 100ns, the outputs will be disabled and will remain

off until OPDIS is reset via the control interface and the end of a processing frame is reached (Table

49).

The output disable register (OPDISR) also allows the PWM outputs to be disabled via a register

write. If OPDISR is set the PWM outputs will be disabled at the end of the next processing frame and

enabled if OPDISR is reset at the end of the next processing frame.

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