WM8602SEDSSLASHV datasheet(18/46 Pages) WOLFSON

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WM8602

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PP Rev 1.5 May 2004

No BCLK edges are allowed between the data words.

MODE

INPUT FORMAT (ORDER)

SUPPORTED MODES

Stereo

L, R

No restrictions apply

Table 10 DSP Mode Input Format

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master/slave mode are summarised

below. MS selects audio interface operation in master or slave mode. In Master mode BCLK and

LRCLK are outputs and the frequency of LRCLK is set by the sample rate control bits SR[3:0]. In

Slave mode BCLK and LRCLK are inputs (refer to Table 12 for sample rate control in this case).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

BCLKINV

BCLK invert bit (for master and slave

modes)

0 = BCLK not inverted

1 = BCLK inverted

Master / Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

LRSWAP

Left/Right channel swap

1 = swap left and right data in audio

interface

0 = output left and right data as normal

LRP

Right, left and I

2S modes – LRCLK

polarity

1 = invert LRCLK polarity

0 = normal LRCLK polarity

(as show in e.g. Figure 12)

DSP Mode – A/B select

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

3:2

WL[1:0]

Audio Data Word Length

11 = 32 bits (see Note)

10 = 24 bits

01 = 20 bits

00 = 16 bits

R2 (02h)

Audio IF

Format

1:0

FORMAT[1:0]

Audio Data Format Select

11 = DSP Mode

10 = I

2S Format

01 = Left justified

00 = Right justified

Table 11 Audio Data Format Control

Notes:

Right Justified mode does not support 32-bit data.

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