WM8602SEDSSLASHV datasheet(24/46 Pages) WOLFSON

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WM8602

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PP Rev 1.5 May 2004

Once the WM8602 has acknowledged a correct address, the controller sends the first byte of control

data (B15 to B8, i.e. the WM8602 register address plus the first bit of register data). The WM8602

then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then

sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the

WM8602 acknowledges again by pulling SDIN low.

The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.

After receiving a complete address and data sequence the WM8602 returns to the idle state and

waits for another start condition. If a start or stop condition is detected out of sequence at any point

during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.

SDIN

SCLK

1st register data bit

DEVICE ADDRESS

(7 BITS)

RD / WR

BIT

ACK

(LOW)

CONTROL BYTE 1

(BITS 15 TO 8)

CONTROL BYTE 1

(BITS 7 TO 0)

remaining 8 bits of

STOP

START

ACK

(LOW)

ACK

(LOW)

Figure 18 2-Wire Serial Control Interface

The WM8602 has two possible device addresses, which can be selected using the CSB pin.

CSB STATE

DEVICE ADDRESS

Low

0011010

High

0011011

Table 20 2-Wire MPU Interface Address Selection

INPUT PROCESSOR

The WM8602 supports the production of stereo or 2.1 outputs from stereo inputs according to Table

21.

OUTPUT CONFIGURATIONS

CONFIG

FL OUT

FR OUT

SUB

OUT

Stereo

•

2.1

•

Table 21 Output Configuration

WM8602SEDS/V 데이터시트(PDF) 24 Page - Wolfson Microelectronics plc

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