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WM8602SEDS/V 데이터시트(PDF) 22 Page - Wolfson Microelectronics plc

부품명 WM8602SEDS/V
상세설명  2.1 CHANNEL PWM CONTROLLER
PDF  46 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
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WM8602
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PP Rev 1.5 May 2004
22
SYNCHRONISER
The WM8602 contains a synchroniser circuit to support the synchronisation of an external LRCLK to
the local LRCLK. This mode is only supported in MPEG mode.
The specification of the synchroniser circuit is:
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25
oC, f
XIN = 27MHz, Slave Mode, fs = 48kHz, 24-bit data,
unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Lock time
tlock
<1
2
s
LRCLK frequency offset
foffLRCLK
±1000
±10’000
ppm fs
0.2
ppm/s
LRCLK drift in Lock
driftLRCLK
6
Hz
Table 15 Synchroniser Specification
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0
SYNCEN
1
Synchroniser Enable
0: Disable
1: Enable (in MPEG mode only)
2:1
GMIN[1:0]
10
Minimum Synchroniser Gain
00: minimum gain = 2
0
01: minimum gain = 2
1
10: minimum gain = 2
2
11: minimum gain = 2
3
4:3
GMAX[1:0]
10
Maximum Synchroniser Gain
00: maximum gain = 2
8
01: maximum gain = 2
10
10: maximum gain = 2
12
11: maximum gain = 2
14
R32 (20h)
Synchroniser
(1)
5
HOLD
0
Hold Synchroniser (and SR detect)
1 : Synchroniser in hold mode
Table 16 Synchroniser (1)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R33 (21h)
Synchroniser
(2)
2:0
SYNTO[2:0]
100
Synchroniser Gain time-out
000: 0.2 ms
001: 0.5 ms
010: 1 ms
011: 2 ms
100: 5 ms (default)
101: 10 ms
110: 20 ms
111: 50 ms
Table 17 Synchroniser (2)
The next table illustrates recommendation for the Synchroniser loop gain G (see also Table 16) and
time-out time (Table 17) with respect to the LRCLK frequency and the resulting Synchroniser lock
time.



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