STV3550 datasheet(102/144 Pages) STMICROELECTRONICS

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STV3550

LSB of the register and taken out of the MSB of the programmed data width. This is shown for a

9-bit data frame in Figure 65.

The shift register shifts at the end of each clock cycle. The clock pulse for shifting is presented to it

from the serial clock input.

When a complete data frame has been shifted, the contents of the shift register (i.e. all bits shifted

into the register), is loaded into the receive buffer.

There are some additional controls required on the shifting operation to allow full support of the I²C

bus standard. These are described in Section 7.7.16: I²C Operation.

7.7.7

Clock Edge Detection

In order to generate the correct shifting and latching signals for the parts of the SSC2, correct

detection of the input serial clock edges must occur. It is possible that the input clock edge rates are

very slow (of the order of several hundred nano-seconds), hence it is essential that the edge

detection can cope with noise spikes.

To achieve this, the SSC2 uses a majority sampling approach to detect the clock edges. Four

consecutive samples are taken. The majority value of the first 3 samples is then taken to provide a

previous signal value. The majority of the last 3 samples is used to provide a current signal value. If

Figure 65: Shift Register Operation For 9 Bit Data Frames

Data_out

Data_in

Data_out

Data_in

Shift Direction

LSB

MSB

LSB

MSB

LSB First Direction (SSCHB = 0)

MSB First Direction (SSCHB = 1)

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