STV3550 datasheet(106/144 Pages) STMICROELECTRONICS

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STV3550

Each sample occurs at the CPU clock frequency. The sampling scheme is shown in Figure 68.

The error condition is indicated by the setting of the SSCPE bit in the status register. An interrupt will

be generated if the SSCPEEN bit is set in the interrupt enables register.

The phase error status bit (and the interrupt, if enabled) is cleared by the next read from the receive

buffer.

7.7.14 Interrupt Mechanism

The SSC2 can generate a variety of different interrupts. They can all be enabled or disabled

independently of each other. All the enabled interrupt conditions are OR-ed together to generate a

global interrupt signal. In addition a dedicated interrupt signal is generated for transmit buffer empty

and receive buffer full. An additional combined interrupt signal is generated for the error conditions:-

receive error, transmit error, phase error and baud rate error.

To determine which interrupt condition occurred, a status register, SSCSTAT is provided which

includes a bit for each condition. This is independent of the interrupt enables register, SSCIEN,

which determines whether the condition asserts one or more of the interrupt signals.

7.7.15 Software Reset

A software reset facility is included in order to clear the device if various unexpected conditions

occur. This is useful during software or hardware development as it allows the SSC2 to be reset

without affecting the rest of the chip.

The reset is performed by setting the SSCSR bit in the SSCCON register. While the bit is set the

entire SSC2 functionality will be held in the reset state. That is ALL functionality, except for the

current settings of the SSCCON, SSCI2C, SSCTBUF, SSCSLAD, SSCBRG and SSCIEN registers.

If these are required to be cleared, this can be done by programming these registers while the

SSCSR bit is held high.

When the SSCSR bit is cleared the device will proceed according to the settings of the SSCCON

and SSCI2C registers.

Figure 68: Phase Error Detection

CPU Clock

Serial_clock_in

Serial_data_in

Sampling Points

Phase Error?

YES

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