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MB9BF412RPMC-G-JNE2 데이터시트(PDF) 74 Page - Cypress Semiconductor

부품명 MB9BF412RPMC-G-JNE2
상세설명  32-bit Arm짰 Cortex짰-M3 FM3 Microcontroller
PDF  112 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB9BF412RPMC-G-JNE2 데이터시트(HTML) 74 Page - Cypress Semiconductor

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Document Number: 002-05615 Rev. *D
Page
74 of 112
MB9B410R Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Address delay time
tAV
MCLK
MAD[24:0]
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
MCSX delay time
tCSL
MCLK
MCSX[7:0]
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
tCSH
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
MOEX delay time
tREL
MCLK
MOEX
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
tREH
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
Data set up →
MCLK ↑ time
tDS
MCLK
MADATA[15:0]
VCC ≥ 4.5 V
19
-
ns
VCC < 4.5 V
37
MCLK ↑ →
Data hold time
tDH
MCLK
MADATA[15:0]
VCC ≥ 4.5 V
0
-
ns
VCC < 4.5 V
MWEX delay time
tWEL
MCLK
MWEX
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
tWEH
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
MDQM[1:0]
delay time
tDQML
MCLK
MDQM[1:0]
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
tDQMH
VCC ≥ 4.5 V
1
9
ns
VCC < 4.5 V
12
MCLK ↑ →
Data output time
tODS
MCLK,
MADATA[15:0]
VCC ≥ 4.5 V
MCLK+1
MCLK+18
ns
VCC < 4.5 V
MCLK+24
MCLK ↑ →
Data hold time
tOD
MCLK
MADATA[15:0]
VCC ≥ 4.5 V
1
18
ns
VCC < 4.5 V
24
Note:
− When the external load capacitance = 30 pF.
Invalid
tDQML
tREH
Address
tCSL
tAV
tREL
RD
Address
WD
tDQMH
tWEH
tWEL
tDH
tDS
tOD
tAV
tCSH
tCYCLE
tDQML
tDQMH
tODS
MCLK
MCSX[7:0]
MAD[24:0]
MDQM[1:0]
MWEX
MADATA[15:0]
MOEX



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