5228-DS09-405-R datasheet(27/100 Pages) BOARDCOM

27 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Hardware Signal Definition Table

Page 15

D03

B03

E05

D04

M05

N04

N05

M04

189

190

191

192

LED3{1:8}

O3S

LED3. Active low. The function of this LED

signal can be configured to output one of

ACTIVITY, FULL-DUPLEX, LINK or SPEED

status. For details, see “LED

Modes” on page 29.

Bias

A15

161

160

RDAC

DAC Bias Resistor. Adjusts the current level

of each of the transmit DAC’s. A resistor of

1.24-k

Ω ±1% must be connected between

the RDAC pin and AGND.

A14

162

161

VREF

Voltage Reference. Low-impedance bias pin

driven by the internal band-gap voltage

reference. This pin must be left unconnected

during normal operation.

JTAG

L02

TDI

IPU

Test Mode Select. Serial data input to the

JTAG TAP controller. Sampled on the rising

edge of TCK. If unused, it can be left

unconnected.

L03

TMS

IPU

Test Data Input. Single control input to the

JTAG TAP controller used to traverse the test-

logic state machine. Sampled on the rising

edge of TCK. If unused, it can be left

unconnected.

L05

TCK

IPU

Test Clock. Clock input used to synchronize

the JTAG TAP control and data transfers. If

unused, it can be left unconnected.

K04

TDO

O3S

Test Data Output. Serial data output from the

JTAG TAP Controller. Updated on the falling

edge of TCK. Actively driven both high and

low when enabled, otherwise high

impedance.

K05

TRST#

IPU

Test Reset. Asynchronous active-low reset

input to the JTAG TAP Controller. Must be

held low during power-up to insure the TAP

Controller initializes to the test-logic-reset

state. Can be pulled low continuously when

JTAG functions are not used. Must be held

low for normal operation.

Power

T14

101

102

PLLVDDC

2.5-V, Phase Locked Loop VDD Core,

DVDD

R14

PLLGND

Phase Locked Loop GND

P14

100

101

PLLVDDP

PLL PAD VDD. Tie this to the same supply as

OVDD.

A16

160

159

BIASVDD

2.5-V, Bias VDD

Table 2: Pin Definitions (Cont.)

BCM5228B BCM5228F BCM5228U Pin Label

I/O

Description

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