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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSP56857 데이터시트(PDF) 560 Page - Freescale Semiconductor, Inc |
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DSP56857 데이터시트(HTML) 560 Page - Freescale Semiconductor, Inc |
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560 / 662 page  Application: Date: Programmer: Sheet C 5685X Digital Signal Controller User Manual, Rev. 4 B-58 Freescale Semiconductor 6 of 9 SCI SCI Status Register (SCISR) SCI Status Register (SCISR) Base + $3 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TDRE TIDLE RDRF RIDLE OR NF FE PF 0 0 0 0 0 0 0 RAF Write Reset 00 00 00 00 00 00 00 00 Bits Name Description 15 TDRE Transmit Data Register Empty This bit is set when the transmit shift register receives a character from the SCI Data Register (SCIDR). Clear TDRE by reading SCISR with TDRE set and then writing to SCI data register in normal mode or by writing the SCIDR with TDE set. 0 No character transferred to transmit shift register 1 Character transferred to transmit shift register; transmit data register empty 14 TIDLE Transmitter llde This bit is set when the TDRE flag is set and not data, preamble, or break character is being transmitted. When TIDLE is set, the TXD pin becomes idle (Logic 1). Clear TIDLE by reading the SCI Status Register (SCISR) with TIDLE set and then writing to the SCI Data Register (SCIDR). TIDLE is not generated when a data character, a preamble, or a break is queued and ready to be sent. 0 Transmission in progress 1 No transmission in progress 13 RDRF Receive Data Register Full This bit is set when the data in the receive shift register transfers to the SCI Data Register (SCIDR) Clear RDRF by reading the SCI Status Register (SCISR) with RDRF set and then reading the SCI data register in normal mode or by reading the SCIDR with RDE set. 0 Data not available in SCI data register 1 Received data available in SCI data register denotes Reserved Bits See the following page for continuation of this register |
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