DSP56857 datasheet(561/662 Pages) FREESCALE

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Date:

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Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-59

7 of 9

SCI

SCI Status Register (SCISR) continued

SCI Status Register

(SCISR)

Base + $3

Bits

Read TDRE TIDLE RDRF RIDLE OR

RAF

Write

Reset

denotes Reserved Bits

Bits

Name

Description

RIDLE

Receiver Idle Line

This bit is set when 10 consecutive Logic 1s (if M = 0) or 11 consecutive Logic 1s (if M = 1) appear

on the receiver input. Once the RIDLE flag is cleared (the receiver detects a Logic 0), a valid frame

must again set the RDRF flag before an idle condition can set the RIDLE flag.

Receiver input is either active now or has never become active since the RIDLE flag was

last cleared

Receiver input has become idle (after receiving a valid frame)

Overrun

This bit is set when software fails to read the SCI Data Register (SCIDR) before the receive shift

SCI data register is not affected. Clear OR by reading the SCI Status Register (SCISR) with OR

set and then writing the SCI status register with any value.

No overrun

1Overrun

Noise Flag

This bit is set when the SCI detects noise on the receiver input. The NF bit is set during the same

cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading the

SCI Status Register (SCISR) and then writing the SCI status register with any value.

No noise

1Noise

See the following page for continuation of this register

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